The present disclosure generally relates to analog-to-digital converters (ADCs) and more specifically to reference pre-charging for ADCs.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A two-step subranging ADC architecture performs an analog-to-digital conversion in two steps. FIG. 1 depicts a conventional two-step subranging ADC architecture 100. Architecture 100 includes a coarse ADC 102 and a fine ADC 104. Coarse ADC 102 includes a coarser or poorer resolution than fine ADC 104 and can quickly determine an approximate subrange that a sample of an input analog signal falls within. This narrows the range of analog voltages in which the sample of the input analog signal may correspond. Fine ADC 104 then further defines the analog voltage from within the subrange selected by coarse ADC 102.
The input analog signal is received at a track-and-hold stage (T/H) 106. Track-and-hold stage 106 tracks the input analog signal and stores an input voltage for the sample of the input analog signal. For example, the input analog signal may be sampled for a half clock cycle and the input voltage from the sample is stored for another half clock cycle.
Coarse ADC 102 compares the stored voltage to a plurality of coarse references received from a reference ladder 108. Reference ladder 108 may include a plurality of tap points. Each tap point may be at a different voltage level for each coarse reference. Coarse ADC 102 performs a first comparison of the input voltage to the coarse references to determine a subrange in which the input voltage falls within.
A result of the first comparison is then used to select finer references or finer subdivisions of the selected subrange for fine ADC 104. For example, certain switches in a switch matrix 110 are closed to provide a second subrange of fine references to fine ADC 104. Fine ADC 104 then performs a second comparison of the fine references and the input voltage.
Encoding and digital correction logic 112 uses the results of the first comparison and the second comparison to determine a first digital code and a second digital code. The first and second digital codes are used to determine a digital output for the sample of the input analog signal. For example, the first and second digital codes may be appropriately weighted, error corrected, and combined to generate the digital output, which may be a digital representation of the sample of the input analog signal.
The determination of the first digital code and second digital code each needs to be made within a half clock period, T/2, where T is a clock period. When the sampling rate goes up, the time that coarse ADC 102 needs to make a decision becomes a larger part of its half clock period T/2.
Reference ladder 108 needs time to settle from a voltage level of a previous sample to set up the fine references. FIG. 2 shows a timing diagram for the conventional two-step subranging architecture 100. At each clock cycle, the input analog signal is tracked (T) and held (H). During the hold period, coarse ADC 1-102 makes its decision within a portion of the T/2 period. Then, in the remaining part of the same T/2 period, coarse output encoding, fine reference selection and subsequent setting of the fine reference takes place. When the sampling rate goes up, coarse output encoding, fine reference selection and subsequent setting of the fine reference combined together take a longer part of the T/2 period, which means less time for reference settling is allotted.
The first digital code from coarse ADC 102 is used to select the switches in switch matrix 110. This reproduces a quantized version of the analog input sample that is used to determine the fine references. For example, the quantized version is the input voltage plus a quantization or rounding error. The output of the switch matrix needs to settle to the voltage of the quantized version. The settling time may become a speed bottleneck as ADC resolution and conversion speed become higher due to large loading from the number of switches and comparators in coarse ADC 102 and fine ADC 104.
FIG. 3 depicts a waveform of a conventional method of precharging using architecture 1-100. At 302, the voltage at the output of switch matrix 1-110 is V1, which is the quantized voltage of the previous sample. At 304, coarse ADC 1-102 is strobed. Then, coarse ADC 1-102 performs the comparison as discussed above. At 306, the switches in switch matrix 1-110 are selected based on the first digital code that was determined. The voltage level needed to set up the fine references is a voltage V2 shown at 308. At 310, a fine reference settling time is needed to move the voltage level from V1 to V2 (ΔV). When the last sample was at a significantly different voltage level as the current sample, a large amount of time is dedicated to fine reference settling to move the voltage from V1 to V2.